IP Facts - 1.0 English

DSP Macro LogiCORE IP Product Guide (PG323)

Document ID
PG323
Release Date
2021-01-25
Version
1.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 Versal™ ACAP, UltraScale+™ , UltraScale™ , Zynq®-7000 SoC, 7 series
Supported User Interfaces N/A
Provided with Core
Design Files Encrypted RTL
Example Design Not Provided
Test Bench Not Provided
Constraints File Not Provided
Simulation Model Encrypted VHDL
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry

Vivado® Design Suite

System Generator for DSP

Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: N/A
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.