Implementation Page - 1.0 English

DSP Macro LogiCORE IP Product Guide (PG323)

Document ID
PG323
Release Date
2021-01-25
Version
1.0 English
Input Port Properties
Specifies the bit-width of the D, A, B, CONCAT and C input ports.
Output Port Properties
Specifies the precision of the P output port; Full Precision and User Defined.
The Vivado® IDE automatically calculates the full precision output width given the width of the specified input ports. When P has been used as an operand, the full precision output width is set to the full DSP Slice width of 48 bits for 7 series and UltraScale™ devices or 58 bits for Versal™ devices. When Full Precision is selected, the output width is set to the full precision value. When User Defined is selected, the output width can be set to any value up to 48 bits and 58 bits for Versal™ . When the specified value is less than the full precision width, the output is truncated, that is, the LSBs are removed. This option should be used when a rounding function has been specified.
Width
Specifies the actual output width of the P output port. When specified to be less than Full Precision, the DSP Slice output is truncated.
Additional Ports
Specifies if the core has a CARRYOUT output port or the ACOUT, BCOUT, PCOUT or CARRYCASCOUT cascaded output ports.
Use DSP Slice
Specifies if the core implementation uses an DSP Slice or device logic equivalent. When a device logic implementation is specified, the core is unlikely to achieve the same Fmax as DSP Slice.