Port Descriptions - 1.0 English

DSP Macro LogiCORE IP Product Guide (PG323)

Document ID
PG323
Release Date
2021-01-25
Version
1.0 English

The core signal ports are shown in the following table.

Table 1. Core Signal Pinout
Port Name I/O Description
CLK 1 I Clock – active rising edge.
CE I Clock Enable – core clock enable (active-High).
SCLR I Synchronous Clear – synchronous reset (active-High). Asserting SCLR synchronously with CLK resets all registers. SCLR has priority over CE.
D [d_width-1:0] I D port – primary input to DSP Slice pre-adder. The maximum d_width is 25 bits for 7 series devices and 27 bits for UltraScale™ and Versal™ devices.
A [a_width-1:0] I A port – input to DSP Slice multiplier and secondary input (subtrahend) to pre-adder. The maximum a_width is 25 bits for 7 series devices and 27 bits for UltraScale and Versal devices.
ACIN [ac_width:0] I Cascaded A port – used as per the A port but must be driven by the ACOUT of the previous DSP Slice, avoids routing and logic. Static selection between A and ACIN is made by the specified DSP Macro instructions. The maximum ac_width is 25 bits for 7 series devices and 27 bits for UltraScale and Versal devices, signed-extended to 30 bits for UltraScale and to 34 bits for Versal.
B [b_width-1:0] I

B port – second input to multiplier.

Maximum b_width: 18 bits for 7 series and UltraScale devices and 24 bits for Versal devices.

BCIN [bcin_width-1:0] I

Cascaded B port. Must be driven by the BCOUT of the previous DSP Slice. Static selection between B and BCIN.

Fixed bcin_width: 18 bits for 7 series and UltraScale devices and 24 bits for Versal devices.

CONCAT

[concat_width-1:0]

I

CONCAT port – concatenation of the A and B DSP Slice inputs. The D input is included in the concatenation. Input to second stage add/sub. Mutually exclusive to the A,B and D ports. The maximum concat_width is 48 bits for 7 series and UltraScale devices and 58 bits for Versal devices.

Note: The A port, when specified, can be passed directly to the add/sub.

C [c_width-1:0] I

C port – input to DSP Slice add/sub.

Maximum c_width: 48 bits for 7 series and UltraScale devices and 58 bits for Versal devices.

PCIN [pcin_width-1:0] I

PCIN port – cascaded P input from the previous DSP Slice. Input to add/sub. Avoids device routing and provides a low latency path.

Fixed pcin_width: 48 bits for 7 series and UltraScale devices and 58 bits for Versal devices.

CARRYIN I CARRYIN port – carry input from device logic, single bit.
CARRYCASCIN I CARRYCASCIN port - cascaded carry input from the previous DSP Slice. Can be used to construct large adders.
SEL [sel_width-1:0] I

SEL port - selects from the enumerated list of instructions specified in the core user interface. Unsigned.

Fixed sel_width: ceil(log2(num_instructions))

CED1..3 I Clock enables for D path registers (active-High)
CEA1..4 I Clock enables for A path registers (active-High)
CEB1..4 I Clock enables for B path registers (active-High)
CECONCAT3..5 I Clock enables for CONCAT path registers (active-High)
CEC1..5 I Clock enables for C path registers (active-High)
CEM I Clock enables for M path registers (active-High)
CEP I Clock enables for P path registers (active-High)
CESEL1..5 I Clock enables for SEL path registers (active-High)
SCLRD I Synchronous reset for D path registers (active-High)
SCLRA I Synchronous reset for A path registers (active-High)
SCLRB I Synchronous reset for B path registers (active-High)
SCLRCONCAT I Synchronous reset for CONCAT path registers (active-High)
SCLRC I Synchronous reset for C path registers (active-High)
SCLRM I Synchronous reset for M path registers (active-High)
SCLRP I Synchronous reset for P path registers (active-High)
SCLRSEL I Synchronous reset for SEL path registers (active-High)
P [p_msb-p_lsb:0] 1 O

P port - output from DSP Slice add/sub, provides the result of the selected instruction.

Maximum p_msb: 47 bits for 7 series and UltraScale devices and 57 bits for Versal devices

Note: p_msb and p_lsb are derived from the Output Port Properties; Full Precision Width and Width. See Implementation for more details.
CARRYOUT O CARRYOUT port - carryout to device logic from add/sub.
ACOUT [ac_width-1:0] O ACOUT port - optional cascade A output, ac_width defined for ACIN.
BCOUT [bc_width-1:0] O BCOUT port - optional cascade B output, bc_width defined for BCIN.
PCOUT [pc_width-1:0] O PCOUT port - optional cascade P output, pc_width defined for PCIN.
CARRYCASCOUT O CARRYCASCOUT port - optional cascade carryout output.
  1. All signals are optional with the exception of CLK and P[p_msb-p_lsb:0].