RNDMACC(arg) - 1.0 English

DSP Macro LogiCORE IP Product Guide (PG323)

Document ID
PG323
Release Date
2021-01-25
Version
1.0 English

When performing symmetric rounding towards infinity of MACC and add accumulate operations, it is difficult to determine the sign of the output ahead of time, so the round might cost an extra clock cycle. This extra cycle can be eliminated by adding the C input rounding constant (typically a binary value of 0.0111…) on the very first cycle. The sign bit of the last but one cycle of the accumulator can be used for the final rounding operation done in the final accumulate cycle. This implementation is a practical way to save a clock cycle. There is a rare chance that the final accumulate operation can flip the sign of the output from the previous accumulated value.

To perform this for a MACC operation, the following DSP Macro instructions are used:

P = (A+D)*B+C (first cycle only)

P = (A+D)*B+P (middle cycles)

P = RNDMACC((A+D)*B+P) (last cycle only)