Tab 3: Implementation - 1.0 English

DSP Macro LogiCORE IP Product Guide (PG323)

Document ID
PG323
Release Date
2021-01-25
Version
1.0 English

The Implementation tab is used to define implementation options. See the Implementation Page for details of all the core parameters on this tab.

Output Port Properties
Specifies the precision of the P output port: Full Precision and User Defined.

The core automatically calculates the full precision output width and binary point position given the width and binary point of the specified input ports. When P has been used as an operand, the full precision output width is set to the full DSP Slice width of 48 bits for 7 series and UltraScaleâ„¢ devices and 58 bits for Versalâ„¢ devices.

When Full Precision is selected, the output is set to full precision width and binary point.

When User Defined is selected, the output width can be set to any value up to 48 bits for 7 series and UltraScale Devices and 58 bits for Versal devices. The output formatting has two modes of operation.
  • Full precision binary point is calculated to be zero.
    • When the output width is specified to be less than the full precision width, the output is truncated, that is, the LSBs are removed.
  • Full precision binary point is calculated to be greater than zero.
    • The binary point is anchored. The output of the core behaves in the same manner as a System Generator Convert block with the following settings: Quantization > Truncate and Overflow > Wrap. Some restrictions on the binary point values are enforced; it cannot be greater than the full precision binary point value and its permitted minimum value will be modified to ensure that when the binary point value and output width are combined, the resulting MSB value does not exceed 48 bits for 7 series and UltraScale devices and 58 bits for Versal devices.
Width
Specifies the user-defined output width of the P output port.
Binary Point
Specifies the user-defined binary point of the P output port.
ce
Selects either a global clock enable pin, or separate clock enable pins for each register. When separate clock enable pins are selected, these are managed within System Generator to correctly handle multirate constraints.
rst
Selects either a global reset pin, or separate reset pins for each datapath. In a similar way to the separate clock enable pins, System Generator manages the situation where datapaths with separate reset controls have different rates.
FPGA Area Estimation
See the System Generator for DSP documentation for detailed information about this section