Accessing 64-bit DDR Memory Location - 1.2 English

Multi-Scaler LogiCORE IP Product Guide (PG325)
Document ID
PG325
Release Date
2023-12-20
Version
1.2 English
Perform the following to access 64-bit DDR memory location:
  1. Change the IP address width to 64-bit in the Customize IP dialog box.
  2. In AMD Vivado™ address editor, unmap the HP0_DDR_LOW base name which has 0x0000_0000 offset address with 2G band.
  3. Auto assign addresses to map DDR_LOW and DDR_HIGH address spaces for 64-bit mode.
  4. Vivado will get DDR_HIGH offset address as 0x0000_0008_0000_0000 with 32G band. The IP can use any address as source/destination buffer address.
Note: Maximum number of inputs and outputs supported by the IP is based on the Maximum Outputs parameter which is configured via the Customize IP dialog box. For example, if the Maximum Outputs parameter is set to 8, it means that the IP has 8 inputs (8 source buffer registers) and 8 outputs (8 destination buffer registers). The combinations (specified in terms of inputs:outputs) like 1:8, 2:8, 3:8 till 8:8 are valid. For example, in 1:8, the application writes same source buffer address in all the 8 source buffer registers.