Common Interface Signals

Common Interface Signals - 1.2 English

Multi-Scaler LogiCORE IP Product Guide (PG325)

Document ID

PG325

Release Date

2023-12-20

Version

1.2 English

Table 1. Common Interface Signals
Signal Name	I/O	Width	Description
`ap_clk`	I	1	Video core clock
`ap_rst_n`	I	1	Video core active-Low reset
`interrupt`	O	1	Interrupt Request Pin

The ap_clk and ap_rst_n signals are shared between the core, memory mapped AXI4 data interfaces, and the AXI4-Lite control interface.

ap_clk: The memory mapped AXI4, and AXI4-Lite interfaces must be synchronous to the core clock signal ap_clk. All memory mapped AXI4 interface input signals and AXI4-Lite control interface input signals are sampled on the rising edge of ap_clk.
ap_rst_n: The ap_rst_n pin is an active-Low, synchronous reset input pertaining to both AXI4-Lite and memory mapped AXI4 interfaces. When ap_rst_n is set to 0, the core resets at the next rising edge of ap_clk.
interrupt: The interrupt status output bus can be integrated with an external interrupt controller that has independent interrupt enable/mask, interrupt clear, and interrupt status registers that allow interrupt aggregation to the system processor.