Example Design - 1.2 English

Multi-Scaler is a memory based scaler. In this example design the Multi-Scaler reads the pattern written by the user to the source buffer of the memory, scales it, and writes it to the destination buffer of the memory, after which the Multi-Scaler generates an interrupt which is connected to the AMD Zynq™ UltraScale+™ MPSoC.

The application code will read the destination buffer before scaling, writes a specific pattern to the source buffer, programs the parameters provided by the user in to the hardware registers and starts the IP. The Multi-Scaler IP reads the pattern that was written in to the source buffer, scales it, and writes it in to the destination buffer. After all the outputs are generated, the Multi-Scaler IP generates a interrupt and this invokes the interrupt handler which reads the contents of the destination buffer and verifies that the scaled data is available in the destination buffer is the correct.

This chapter provides an example system that includes the Video Multi-Scaler. Important system-level aspects when designing with the Video Multi-Scaler are highlighted in these example designs, including the following:

• The Video Multi-Scaler
• Typical usage of the Video Multi-Scaler with other cores and usage with memory mapped AXI4 interface memory buffers.
• Configuration of the Video Multi-Scaler by programming the registers.

The supported platforms are listed in the following table.

Multi-Scaler is a memory based scaler, in this example design the Multi-Scaler reads the pattern written by the user to the source buffer of the memory, scales it and writes it to the destination buffer of the memory, after that Multi-Scaler generates an interrupt which is connected to the Zynq UltraScale+ MPSoC.

The application code will read the destination buffer before scaling, writes a specific pattern to the source buffer, programs the parameters provided by the user in to the hardware registers and starts the IP. Multi-Scaler IP reads the pattern that was written in to the source buffer, scales it and writes it in to the destination buffer. After all the outputs are generated, Multi-Scaler IP generates a interrupt and this invokes the interrupt handler which reads the contents of the destination buffer and verifies that the scaled data available in the destination buffer is the correct.

To open the example project, perform the following:

1. Select the Video Multi-Scaler IP from the Vivado IP catalog.
2. Double-click the selected IP or right-click the IP and select Customize IP from the menu.
3. Configure the build-time parameters in the Customize IP window and click OK. The Vivado IDE generates an example design matching the build-time configuration.
4. In the Generate Output Products window, select Generate or Skip. If Generate is selected, the IP output products are generated after a brief moment.
5. Right-click Video Multi-Scaler in the Sources panel, and select Open IP Example Design from the menu.
6. In the Open IP Example Design window, select example project directory, and click OK.

The Vivado software then runs automation to generate the example design in the selected directory. The generated project contains a synthesizable example design. The following figure shows the Source panel of the example project. Synthesizable example block design, along with top-level file, resides in the Design Sources catalog.