- Memory mapped AXI4 Interface
- Supports maximum eight outputs
- Supports spatial resolutions from 64 × 64 up to 8192 × 4320
- Supports one, two, or four pixel-width
- Supports RGB, YUV 444, YUV 422, YUV 420
- Supports 8-bit and 10-bit per color component on memory interface
- Supports semi-planar memory formats next to packed memory formats
- Dynamically configurable source and destination buffer addresses
- Supports 6, 8, 10, and 12 taps in both H and V domains
- Supports 64 phases
- Supports 32-bit and 64-bit DDR memory address access