AMD LogiCORE™ IP Facts Table | |
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Core Specifics | |
Supported Device Family 1 | AMD Versal™ Adaptive SoCs, AMD UltraScale+™ , AMD UltraScale™ , 7 series FPGAs, AMD Zynq™ 7000 SoC |
Supported User Interfaces | AXI Master Lite, AXI4-Lite |
Resources | Performance and Resource Use web page |
Provided with Core | |
Design Files | Not Provided |
Example Design | Verilog |
Test Bench | Not Provided |
Constraints File | XDC |
Simulation Model | Encrypted RTL |
Supported S/W Driver 2 | Standalone Linux V4L2 MEM2MEM |
Tested Design Flows 3 | |
Design Entry | AMD Vivado™ Design Suite |
Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
Synthesis | Vivado Synthesis |
Support | |
Release Notes and Known Issues | Master Answer Record: 70292 |
All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
Support web page | |
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