This appendix provides details about how this IP core was tested for compliance with the protocol to which it was designed.
Simulation
A highly parameterizable test bench was used to test the Video Multi-Scaler in AMD Vitis™ High-Level Synthesis (HLS). Testing included the following:
- Register accesses
- Processing multiple frames of data
- Varying IP throughput and pixel data width
- Testing the Video Multi-Scaler with memory mapped AXI4 interface
- Testing of various frame sizes
- Varying parameter settings
- Generating multiple outputs
Hardware Testing
The Video Multi-Scaler core has been validated at AMD to represent many different parameterizations. A test design was developed for the core that incorporated an AMD Zynq™ UltraScale+™ MPSoC processor, AXI4-Lite interconnect, and various other peripherals. The Zynq UltraScale+ MPSoC processor is responsible for the following functions:
- Programing the video Multi-Scaler IP registers.
- Launching the test.
- Reporting the Pass/Fail status of the test and any errors that were found.