The Embedded Memory Generator core supports dual-port RAM implementations. Each port is equivalent and independent, yet they access the same memory space. In such an arrangement, it is possible to have data collisions. The ramifications of this behavior are described for both asynchronous and synchronous clocks.
Collisions and Synchronous Clocks: General Guidelines
Synchronous clocks cause a number of special case collision scenarios. Using asynchronous clocks, when one port writes data to a memory location, the other port must not read or write that location for a specified amount of time. This time (clock-to-Q, TCQ) is defined in the device data sheet, along with other block RAM/UltraRAM switching characteristics.
- Synchronous Write-Write Collisions
- A write-write collision occurs if both ports attempt to write to the same location in memory. The resulting contents of the memory location are unknown. The write-write collisions affect memory content, as opposed to write-read collisions which only affect data output.
- Using Byte-Writes
- When using byte-writes, memory contents are not corrupted when separate bytes are written in the same data word. RAM contents are corrupted only when both ports attempt to write the same byte. The following figure illustrates this case. Assume addra = addrb = 0.
- Synchronous Write-Read Collisions
- A synchronous write-read collision might occur if a port attempts to write a
memory location and the other port reads the same location. While memory
contents are not corrupted in write-read collisions, the validity of the
output data depends on the write port operating mode.
- If the write port is in the read first mode, the other port can reliably read the old memory contents.
- If the write port is in the write first or no change mode, data on the output of the read port is invalid.
- In the case of byte-writes, only updated bytes are invalid on the read port output.
The following figure illustrates write-read collisions and the
effects of byte-writes.
doutb is shown for when
port A is in the write first mode and the read first mode. Assume
= 0, port B is always reading, and
all memory locations are initialized to 0. The RAM contents are never corrupted in
Collisions and Simple Dual-port RAM
For simple dual-port RAM, the operating modes read first, write first, and no change are available irrespective of clocking.
The simple dual-port RAM is like a true dual-port RAM where only the Write interface of the A port and the read interface of B port are connected. The operating modes define the write-to-read relationship of the A or B ports, and only impact the relationship between A and B ports during an address collision.
For synchronous clocking and during a collision, the write mode of port A can be configured so that a read operation on port B either produces data (acting like read first), or produces undefined data (Xs). For this reason, it is always advised to use read first when configured as a simple dual-port RAM. For asynchronous clocking, Xilinx recommends setting the write mode of port A to write first for collision safety.