Customizing and Generating the Core - 1.0 English

Embedded Memory Generator LogiCORE IP Product Guide (PG326)

Document ID
PG326
Release Date
2023-06-14
Version
1.0 English

This section includes information about using AMD tools to customize and generate the core in the AMD Vivado™ Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.

The following section defines the possible customization options in the Embedded Memory Generator core Vivado IDE. The Native Interface Embedded Memory Generator core Vivado IDE includes the following tabs: