doutb) can have different widths, as described in the following sections.
The limitations of the data width aspect ratio feature (some of which are imposed by other optional features) are described in the following sections. The Vivado® IP integrator GUI ensures only valid aspect ratios are selected.
Port Aspect Ratios
The Embedded Memory Generatorcore supports port aspect ratios of 1:32, 1:16, 1:8, 1:4, 1:2, 1:1, 2:1, 4:1, 8:1, 16:1, and 32:1. The port A data width can be up to 32 times larger than the port B data width, or vice versa. The smaller data words are arranged in little-endian format
Port Aspect Ratio Example
addrabus is 11 bits, while the
addrbbus is 13 bits. The data is stored little-endian, as shown in the following figure.
Read-to-Write Aspect Ratios
When implementing RAMs, the Embedded Memory Generator core allows read and write aspect ratios on either port. On each port A and port B, the Read to Write data width ratio of that port can be 1:32, 1:16, 1:8, 1:4, 1:2, 1:1, 2:1, 4:1, 8:1, 16:1, or 32:1.
Because the read and write interfaces of each port can differ, it is
possible for all four data buses (
doutb) of True Dual-port RAMs to have a
different width. The maximum ratio between any two data buses is 32:1. The widest
data bus can be no larger than 4096 bits.
If the read and write data widths on a port are different, the memory depth is different with respect to read and write accesses. For example, if the read interface of port A is twice as wide as the write interface of port B, then it is also half as deep. The ratio of the widths is always the inverse of the ratio of the depths. For the shallower interface, the least significant bits of the address bus are ignored. The data words are arranged in little-endian format.
Aspect Ratio Limitations
In general, no port data width can be wider than 4096 bits, and no two data widths can have a ratio greater than 32:1. However, when using byte-writes, no two data widths can have a ratio greater than 4:1.