Feature Summary - 1.0 English

Embedded Memory Generator v1.0 LogiCORE IP Product Guide (PG326)

Document ID
Release Date
1.0 English

The Embedded Memory Generator core uses embedded block RAM/UltraRAM and Distributed RAM to generate five types of memories:

  • Single-port RAM
  • Simple dual-port RAM
  • True dual-port RAM
  • Single-port ROM
  • Dual-port ROM

For dual-port memories, each port operates independently. Operating mode, optional read latency, and optional pins are selectable per port. For simple dual-port RAM, the operating modes are not selectable. See Collision Behavior for additional information.

Configurable Width and Depth

The Embedded Memory Generator core can generate memory structures up to 50 megabits.

Selectable Operating Mode per Port

The Embedded Memory Generator core supports the following operating modes: Write first, read first, and no change. Each port can be assigned its own operating mode.

Selectable Port Aspect Ratios

The core supports the aspect ratios across the ports only when:
  • The A port width might differ from the B port width by a factor of 1, 2, 4, 8, 16, or 32.
  • The read width might differ from the write width by a factor of 1, 2, 4, 8, 16, or 32 for each port. The maximum ratio between any two of the data widths (dina → doutb, dinb → douta) is 32:1.

Optional Byte-Write Enable

The Embedded Memory Generator core provides byte-write support for memory widths which are multiples of eight (no parity) or nine bits (with parity).

Optional Output Registers (Read Latency A/B)

The Embedded Memory Generator core provides up to 64 stages of pipeline registers to increase memory performance. The output registers for port A and port B can be chosen separately. The core supports the built-in block RAM/UltraRAM output registers as well as registers implemented in the FPGA general interconnect.

Memory Initialization

The memory contents can be optionally initialized using a memory initialization (MEM) file or by using the default data option. A MEM file can define the initial contents of each individual memory location, while the default data option defines the initial content of all locations.

For more details, see Update MEM to Update Bit Files with MMI and ELF Data in Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898).

Hamming Error Correction Capability

Simple dual-port RAM memories support the built-in FPGA Hamming Error Correction Capability (ECC) available block RAM/UltraRAM primitives for data widths greater than 64 bits. The built-in ECC (ECC) memory automatically detects single-bit and double-bit errors, and is able to auto-correct the single-bit errors.