|
Core Specifics |
| Supported Device Family
1
|
Versal™
ACAP |
| Supported User Interfaces |
Memory Interface |
| Provided
with Core
|
| Design Files |
System Verilog |
| Example Design |
N/A |
| Test Bench |
N/A |
| Constraints File |
N/A |
| Simulation Model |
N/A
2
|
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
IP integrator
|
| Simulation |
For supported simulators, see the
Xilinx Design Tools: Release Notes
Guide
. |
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change
Logs |
Master Vivado IP Change Logs: 72775
|
|
Xilinx Support web page
|
- For a complete list of
supported devices, see the
Vivado®
IP catalog.
- For the supported versions of
the tools, see the
Xilinx Design Tools:
Release Notes Guide
.
|