Vivado Synthesis Infers RAMs using homogeneous memory resources per RTL memory. So an RTL RAM is implemented using all URAMs or all BRAMs or all LUTRAMs. While this keeps the implementation simple, there are scenarios where this leads to sub-optimal resource usage. This happens specifically when RTL memory depth is non-power-of 2 of address size and/or RTL memory width is not aligned with the primitive width. This becomes prominent in Versal architecture with removal of X1, X2 and X4 widths of BRAM width. So any RTL RAM width not divisible by 9 will lead to inefficient utilization of BRAMs/URAMs with empty space that leads to more URAM/BRAM resources. Mixed RAM is to solve this problem by using multiple memory resource types to implement a RTL memory.
For details, see Vivado Design Suite User Guide: Synthesis (UG901).