Register Clock Enable Pins - 1.0 English

Embedded Memory Generator LogiCORE IP Product Guide (PG326)

Document ID
PG326
Release Date
2023-06-14
Version
1.0 English

The output registers are controlled by the regcea/regceb pins; the data output from the core can be controlled independent of the flow of data through the rest of the core. When using the regce pin, the last output register operates independent of the en signal.