Verification, Compliance, and Interoperability - 1.0 English

Embedded Memory Generator LogiCORE IP Product Guide (PG326)

Document ID
PG326
Release Date
2023-06-14
Version
1.0 English

The Embedded Memory Generator core and the associated XPM libraries are rigorously verified using advanced verification techniques, including a constrained random configuration generator and a cycle-accurate bus functional model.

Simulation

The Embedded Memory Generator core has been tested with the AMD Vivado™ Design Suite, Xilinx XSIM, Cadence Incisive Enterprise Simulator (IES), Synopsys VCS and VCS MX, and Mentor Graphics Questa SIM.