AXI FIFO Feature Overview - 1.0 English

Easy Integration of Independent FIFOs for Read and Write Channels

For AXI memory mapped interfaces, AXI specifies Write Channels and Read Channels. Write Channels include a Write Address Channel, Write Data Channel and Write Response Channel. Read Channels include a Read Address Channel and Read Data Channel. The Embedded FIFO Generator core provides the ability to generate either Write Channels or Read Channels, or both Write Channels and Read Channels for AXI memory mapped. Three FIFOs are integrated for Write Channels and two FIFOs are integrated for Read Channels. When both Write and Read Channels are selected, the FIFO Generator core integrates five independent FIFOs.

For AXI memory mapped interfaces, the Embedded FIFO Generator core provides the ability to implement independent FIFOs for each channel, as shown in the following figure. For each channel, the core can be independently configured to generate a block RAM or Distributed Memory or UltraRAM based FIFO. The depth of each FIFO can also be independently configured.

Figure 1. AXI Memory Mapped FIFO Block Diagram

Clock and Reset Implementation and Operation

For the AXI4-Stream and AXI memory mapped interfaces, all instantiated FIFOs share clock and asynchronous active-Low reset signals. In addition, all instantiated FIFOs can support either independent clock or common clock operation.

The independent clock configuration of the Embedded FIFO Generator core enables you to implement unique clock domains on the write and read ports. The Embedded FIFO Generator core handles the synchronization between clock domains, placing no requirements on phase and frequency. When data buffering in a single clock domain is required, the Embedded FIFO Generator core can be used to generate a core optimized for a single clock by selecting the common clock option.

Automatic FIFO Width Calculation

AXI FIFOs support symmetric widths for the FIFO Read and Write ports. The FIFO width for the AXI FIFO is determined by the selected interface type (AXI4-Stream or AXI memory mapped) and user-selected signals and signal widths within the given interface. The AXI FIFO width is then calculated automatically by the aggregation of all signal widths in a respective channel.

Supported Configuration, Memory and Application Types

The Embedded FIFO Generator core implements FIFOs built from block RAM, UltraRAM, or Distributed RAM memory types. Depending on the application type selection (Data FIFO or Packet FIFO), the core combines memory primitives in an optimal configuration based on the calculated width and selected depth of the FIFO.

Packet FIFO

The Packet FIFO configuration delays the start of packet (burst) transmission until the end (LAST beat) of the packet is received. This ensures uninterrupted availability of data after master-side transfer begins, thus avoiding source-end stalling of the AXI data channel. This is valuable in applications in which data originates at a master device. Examples of this include real-time signal channels that operate at a lower data rate than the downstream AXI switch and/or slave destination, such as a high-bandwidth memory.

The Packet FIFO principle applies to both AXI4 memory-mapped burst transactions (both write and read) and AXI4-Stream packet transmissions. This feature is sometimes referred to as "store-and-forward", referring to the behavior for memory-mapped writes and stream transmissions. For memory-mapped reads, transactions are delayed until there are enough vacancies in the FIFO to guarantee uninterrupted buffering of the entire read data packet, as predicted by the AR-channel transaction. Read transactions do not actually rely on the RLAST signal.

The Packet FIFO feature is supported for Common Clock AXI4 and Common/Independent Clock AXI4-Stream configurations. It is not supported for AXI4-Lite configurations.

AXI4-Stream Packet FIFO

The Embedded FIFO Generator core uses AXI4-Stream Interface for the AXI4-Stream Packet FIFO feature. The Embedded FIFO Generator core indicates a tvalid on the AXI4-Stream Master side when a complete packet (marked by tlast) is received on the AXI4-Stream Slave side or when the AXI4-Stream FIFO is FULL. Indicating tvalid on the Master side due to the FIFO becoming full is an exceptional case, and in such case, the Packet FIFO acts as a normal FWFT FIFO forwarding the data received on the Slave side to the Master side until it receives tlast on the Slave side.

AXI4 Packet FIFO

Error Injection and Correction (ECC) Support

The block RAM and UltraRAM macros are equipped with built-in Error Injection and Correction Checking. This feature is available for both the common clock block/UltraRAM FIFOs and independent clock block RAM FIFOs.

AXI Slave Interface for Performing Writes

AXI FIFOs provide an AXI Slave interface for performing Writes. The AXI Master provides INFORMATION and VALID signals; the AXI FIFO accepts the INFORMATION by asserting the READY signal. The READY signal is de-asserted only when the FIFO is full.

AXI Master Interface for Performing Reads

The AXI FIFO provides an AXI Master interface for performing Reads. The AXI FIFO provides INFORMATION and VALID signals; upon detecting a READY signal asserted from the AXI Slave interface, the AXI FIFO places the next INFORMATION on the bus. The VALID signal is de-asserted only when the FIFO is empty.