AXI FIFO Interface Signals

Global Signals

The following table defines the global interface signals for AXI FIFO.

The s_aresetn signal causes a reset of the entire core logic. It is an active-Low, asynchronous input synchronized internally in the core before use. The initial hardware reset should be generated by the user.

Table 1. AXI FIFO - Global Interface Signals
Name	Direction	Description
Global Clock and Reset Signals Mapped to FIFO Clock and Reset Inputs
m_aclk	Input	Global Master Interface Clock: All signals on Master Interface of AXI FIFO are synchronous to m_aclk
s_aclk	Input	Global Slave Interface Clock: All signals are sampled on the rising edge of this clock.
s_aresetn	Input	Global Reset: This signal is active-Low.

AXI4-Stream FIFO Interface Signals

The following table defines the AXI4-Stream FIFO interface signals.

Table 2. AXI4-Stream FIFO Interface Signals
Name	Direction	Description
AXI4-Stream Interface: Handshake Signals for FIFO Write Interface
s_axis_tvalid	Input	TVALID: Indicates that the master is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.
s_axis_tready	Output	TREADY: Indicates that the slave can accept a transfer in the current cycle.
AXI4-Stream Interface: Information Signals Mapped to FIFO Data Input (din) Bus
s_axis_tdata[m-1:0]	Input	TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes.
s_axis_tstrb[m/8-1:0]	Input	TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b, DATA[63:56] is not valid
s_axis_tkeep[m/8-1:0]	Input	TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes and can be removed from the data stream. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: KEEP[0] = 0b, DATA[7:0] is a NULL byte KEEP [7] = 1b, DATA[63:56] is not a NULL byte
s_axis_tlast	Input	TLAST: Indicates the boundary of a packet.
s_axis_tid[m:0]	Input	TID: The data stream identifier that indicates different streams of data.
s_axis_tdest[m:0]	Input	TDEST: Provides routing information for the data stream.
s_axis_tuser[m:0]	Input	TUSER: The user-defined sideband information that can be transmitted alongside the data stream.
AXI4-Stream Interface: Handshake Signals for FIFO Read Interface
m_axis_tvalid	Output	TVALID: Indicates that the master is driving a valid transfer. A transfer takes place when both tvalid and tready are asserted.
m_axis_tready	Input	TREADY: Indicates that the slave can accept a transfer in the current cycle.
AXI4-Stream Interface: Information Signals Derived from FIFO Data Output (dout) Bus
m_axis_tdata[m-1:0]	Output	TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes.
m_axis_tstrb[m/8-1:0]	Output	TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b, DATA[63:56] is not valid
m_axis_tkeep[m/8-1:0]	Output	TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes and can be removed from the data stream. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: KEEP[0] = 1b, DATA[7:0] is a NULL byte KEEP [7] = 0b, DATA[63:56] is not a NULL byte
m_axis_tlast	Output	TLAST: Indicates the boundary of a packet.
m_axis_tid[m:0]	Output	TID: The data stream identifier that indicates different streams of data.
m_axis_tdest[m:0]	Output	TDEST: Provides routing information for the data stream.
m_axis_tuser[m:0]	Output	TUSER: The user-defined sideband information that can be transmitted alongside the data stream.
AXI4-Stream FIFO: Optional Sideband Signals
injectsbiterr_axis	Input	Inject Single-Bit Error: Injects a single-bit error if the ECC feature is used.
injectdbiterr_axis	Input	Inject Double-Bit Error: Injects a double-bit error if the ECC feature is used.
sbiterr_axis	Output	Single-Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error.
dbiterr_axis	Output	Double-Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.
wr_data_count_axis[d:0]	Output	Write Data Count: This bus indicates the number of words written into the FIFO. The count is guaranteed to never underreport the number of words in the FIFO, to ensure you never overflow the FIFO. The exception to this behavior is when a write operation occurs at the rising edge of write clock; that write operation will only be reflected on wr_data_count at the second rising clock edge. D= log₂(FIFO depth)+1
rd_data_count_axis[d:0]	Output	Read Data Count: This bus indicates the number of words available for reading in the FIFO. The count is guaranteed to never over-report the number of words available for reading, to ensure that you do not underflow the FIFO. The exception to this behavior is when the read operation occurs at the rising edge of read clock; that read operation is only reflected on rd_data_count at the second rising clock edge. D = log₂(FIFO depth)+1
prog_full_axis	Output	Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable threshold. It is deasserted when the number of words in the FIFO is less than the programmable threshold.
prog_empty_axis	Output	Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable threshold. It is deasserted when the number of words in the FIFO exceeds the programmable threshold.

AXI4 FIFO Interface Signals

Write Channels

The following table defines the AXI4 FIFO interface signals for the Write Address Channel.

Table 3. AXI4 Write Address Channel FIFO Interface Signals
Name	Direction	Description
AXI4 Interface Write Address Channel: Information Signals Mapped to FIFO Data Input (din) Bus
s_axi_awid[m:0]	Input	Write Address ID: Identification tag for the write address group of signals.
s_axi_awaddr[m:0]	Input	Write Address: The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
s_axi_awlen[7:0]	Input	Burst Length: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
s_axi_awsize[2:0]	Input	Burst Size: Indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
s_axi_awburst[1:0]	Input	Burst Type: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
s_axi_awlock[1:0]	Input	Lock Type: This signal provides additional information about the atomic characteristics of the transfer.
s_axi_awcache[3:0]	Input	Cache Type: Indicates the bufferable, cacheable, write-through, write-back, and allocate attributes of the transaction.
s_axi_awprot[2:0]	Input	Protection Type: Indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
s_axi_awqos[3:0]	Input	Quality of Service (QoS): Sent on the write address channel for each write transaction.
s_axi_awregion[3:0]	Input	Region Identifier: Sent on the write address channel for each write transaction.
s_axi_awuser[m:0]	Input	Write Address Channel User
AXI4 Interface Write Address Channel: Handshake Signals for FIFO Write Interface
s_axi_awvalid	Input	Write Address Valid: Indicates that valid write address and control information are available: 1 = Address and control information available. 0 = Address and control information not available. The address and control information remain stable until the address acknowledge signal, awready, goes High.
s_axi_awready	Output	Write Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready. 0 = Slave not ready.
AXI4 Interface Write Address Channel: Information Signals Derived from FIFO Data Output (dout) Bus
m_axi_awid[m:0]	Output	Write Address ID: This signal is the identification tag for the write address group of signals.
m_axi_awaddr[m:0]	Output	Write Address: The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
m_axi_awlen[7:0]	Output	Burst Length: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
m_axi_awsize[2:0]	Output	Burst Size: This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
m_axi_awburst[1:0]	Output	Burst Type: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
m_axi_awlock[1:0]	Output	Lock Type: This signal provides additional information about the atomic characteristics of the transfer.
m_axi_awcache[3:0]	Output	Cache Type: This signal indicates the bufferable, cacheable, write-through, write-back, and allocate attributes of the transaction.
m_axi_awprot[2:0]	Output	Protection Type: This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
m_axi_awqos[3:0]	Output	Quality of Service (QoS): Sent on the write address channel for each write transaction.
m_axi_awregion[3:0]	Output	Region Identifier: Sent on the write address channel for each write transaction.
m_axi_awuser[m:0]	Output	Write Address Channel User
AXI4 Interface Write Address Channel: Handshake Signals for FIFO Read Interface
m_axi_awvalid	Output	Write Address Valid: Indicates that valid write address and control information are available: 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes high.
m_axi_awready	Input	Write Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready 0 = Slave not ready

The following table defines the AXI4 FIFO interface signals for the Write Data Channel.

Table 4. AXI4 Write Data Channel FIFO Interface Signals
Name	Direction	Description
AXI4 Interface Write Data Channel: Information Signals mapped to FIFO Data Input (din) Bus
s_axi_wdata[m-1:0]	Input	Write Data: The write data bus can be 8, 16, 32, 64, 128, 256 or 512 bits wide.
s_axi_wstrb[m/8-1:0]	Input	Write Strobes: Indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus. Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)]. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b, DATA[63:56] is not valid
s_axi_wlast	Input	Write Last: Indicates the last transfer in a write burst.
s_axi_wuser[m:0]	Input	Write Data Channel User
AXI4 Interface Write Data Channel: Handshake Signals for FIFO Write Interface
s_axi_wvalid	Input	Write Valid: Indicates that valid write data and strobes are available: 1 = Write data and strobes available. 0 = Write data and strobes not available.
s_axi_wready	Output	Write Ready: Indicates that the slave can accept the write data: 1 = Slave ready 0 = Slave not ready
AXI4 Interface Write Data Channel: Information Signals Derived from FIFO Data Output (dout) Bus
m_axi_wdata[m-1:0]	Output	Write Data: The write data bus can be 8, 16, 32, 64, 128, 256 or 512 bits wide.
m_axi_wstrb[m/8-1:0]	Output	Write Strobes: Indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus. Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)]. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b, DATA[63:56] is not valid
m_axi_wlast	Output	Write Last: Indicates the last transfer in a write burst.
m_axi_wuser[m:0]	Output	Write Data Channel User
AXI4 Interface Write Data Channel: Handshake Signals for FIFO Read Interface
m_axi_wvalid	Output	Write valid: Indicates that valid write data and strobes are available: 1 = Write data and strobes available 0 = Write data and strobes not available
m_axi_wready	Input	Write ready: Indicates that the slave can accept the write data: 1 = Slave ready 0 = Slave not ready
AXI4 Write Data Channel FIFO: Optional Sideband Signals
injectsbiterr_wdch	Input	Inject Single-Bit Error: Injects a single bit error if the ECC feature is used.
injectdbiterr_wdch	Input	Inject Double-Bit Error: Injects a double bit error if the ECC feature is used.
sbiterr_wdch	Output	Single-Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error.
dbiterr_wdch	Output	Double-Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.
wr_data_count_wdch[d:0]	Output	Write Data Count: This bus indicates the number of words written into the FIFO. The count is guaranteed to never underreport the number of words in the FIFO, to ensure you never overflow the FIFO. The exception to this behavior is when a write operation occurs at the rising edge of write clock, that write operation will only be reflected on wr_data_count at the next rising clock edge. D = log₂(FIFO depth)+1
rd_data_count_wdch[d:0]	Output	Read Data Count: This bus indicates the number of words available for reading in the FIFO. The count is guaranteed to never over-report the number of words available for reading, to ensure that you do not underflow the FIFO. The exception to this behavior is when the read operation occurs at the rising edge of read clock, that read operation is only reflected on rd_data_count at the next rising clock edge. D = log₂(FIFO depth)+1
prog_full_wdch	Output	Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable threshold. It is deasserted when the number of words in the FIFO is less than the programmable threshold.
prog_empty_wdch	Output	Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable threshold. It is deasserted when the number of words in the FIFO exceeds the programmable threshold.

The following table defines the AXI4 FIFO interface signals for the Write Response Channel.

Table 5. AXI4 Write Response Channel FIFO Interface Signals
Name	Direction	Description
AXI4 Interface Write Response Channel: Information Signals Mapped to FIFO Data Output (dout) Bus
s_axi_bid[m:0]	Output	Response ID: The identification tag of the write response. The BID value must match the AWID value of the write transaction to which the slave is responding.
s_axi_bresp[1:0]	Output	Write Response: Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
s_axi_buser[m:0]	Output	Write Response Channel User
AXI4 Interface Write Response Channel: Handshake Signals for FIFO Read Interface
s_axi_bvalid	Output	Write Response Valid: Indicates that a valid write response is available: 1 = Write response available. 0 = Write response not available.
s_axi_bready	Input	Response Ready: Indicates that the master can accept the response information. 1 = Master ready. 0 = Master not ready.
AXI4 Interface Write Response Channel: Information Signals Derived from FIFO Data Input (din) Bus
m_axi_bid[m:0]	Input	Response ID: The identification tag of the write response. The BID value must match the AWID value of the write transaction to which the slave is responding.
m_axi_bresp[1:0]	Input	Write Response: Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
m_axi_buser[m:0]	Input	Write Response Channel User
AXI4 Interface Write Response Channel: Handshake Signals for FIFO Write Interface
m_axi_bvalid	Input	Write Response Valid: Indicates that a valid write response is available: 1 = Write response available. 0 = Write response not available.
m_axi_bready	Output	Response Ready: Indicates that the master can accept the response information. 1 = Master ready. 0 = Master not ready.

Read Channels

The following table defines the AXI4 FIFO interface signals for the Read Address Channel.

Table 6. AXI4 Read Address Channel FIFO Interface Signals
Name	Direction	Description
AXI4 Interface Read Address Channel: Information Signals Mapped to FIFO Data Input (din) Bus
s_axi_arid[m:0]	Input	Read Address ID: This signal is the identification tag for the read address group of signals.
s_axi_araddr[m:0]	Input	Read Address: The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
s_axi_arlen[7:0]	Input	Burst Length: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
s_axi_arsize[2:0]	Input	Burst Size: This signal indicates the size of each transfer in the burst.
s_axi_arburst[1:0]	Input	Burst Type: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
s_axi_arlock[1:0]	Input	Lock Type: This signal provides additional information about the atomic characteristics of the transfer.
s_axi_arcache[3:0]	Input	Cache Type: This signal provides additional information about the cacheable characteristics of the transfer.
s_axi_arprot[2:0]	Input	Protection Type: This signal provides protection unit information for the transaction.
s_axi_arqos[3:0]	Input	Quality of Service (QoS): Sent on the read address channel for each read transaction.
s_axi_arregion[3:0]	Input	Region Identifier: Sent on the read address channel for each read transaction.
s_axi_aruser[m:0]	Input	Read Address Channel User
AXI4 Interface Read Address Channel: Handshake Signals for FIFO Write Interface
s_axi_arvalid	Input	Read Address Valid: When high, indicates that the read address and control information is valid and will remain stable until the address acknowledge signal, arready, is high. 1 = Address and control information valid. 0 = Address and control information not valid.
s_axi_arready	Output	Read Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready. 0 = Slave not ready.
AXI4 Interface Read Address Channel: Information Signals Derived from FIFO Data Output (dout) Bus
m_axi_arid[m:0]	Output	Read Address ID: This signal is the identification tag for the read address group of signals.
m_axi_araddr[m:0]	Output	Read Address: The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
m_axi_arlen[7:0]	Output	Burst Length: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
m_axi_arsize[2:0]	Output	Burst Size: This signal indicates the size of each transfer in the burst.
m_axi_arburst[1:0]	Output	Burst Type: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
m_axi_arlock[1:0]	Output	Lock Type: This signal provides additional information about the atomic characteristics of the transfer.
m_axi_arcache[3:0]	Output	Cache Type: This signal provides additional information about the cacheable characteristics of the transfer.
m_axi_arprot[2:0]	Output	Protection Type: This signal provides protection unit information for the transaction.
m_axi_arqos[3:0]	Output	Quality of Service (QoS) signaling, sent on the read address channel for each read transaction.
m_axi_arregion[3:0]	Output	Region Identifier: Sent on the read address channel for each read transaction.
m_axi_aruser[m:0]	Output	Read Address Channel User
AXI4 Interface Read Address Channel: Handshake Signals for FIFO Read Interface
m_axi_arvalid	Output	Read Address Valid: Indicates, when HIGH, that the read address and control information is valid and will remain stable until the address acknowledge signal, arready, is high. 1 = Address and control information valid. 0 = Address and control information not valid.
m_axi_arready	Input	Read Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready. 0 = Slave not ready.

The following table defines the AXI4 FIFO interface signals for the Read Data Channel.

Table 7. AXI4 Read Data Channel FIFO Interface Signals
Name	Direction	Description
AXI4 Interface Read Data Channel: Information Signals Mapped to FIFO Data Output (dout) Bus
s_axi_rid[m:0]	Output	Read ID Tag: ID tag of the read data group of signals. The RID value is generated by the slave and must match the ARID value of the read transaction to which it is responding.
s_axi_rdata[m-1:0]	Output	Read Data: Can be 8, 16, 32, 64, 128, 256 or 512 bits wide.
s_axi_rresp[1:0]	Output	Read Response: Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
s_axi_rlast	Output	Read Last: Indicates the last transfer in a read burst.
s_axi_ruser[m:0]	Output	Read Data Channel User
AXI4 Interface Read Data Channel: Handshake Signals for FIFO Read Interface
s_axi_rvalid	Output	Read Valid: Indicates that the required read data is available and the read transfer can complete: 1 = Read data available. 0 = Read data not available.
s_axi_rready	Input	Read Ready: Indicates that the master can accept the read data and response information: 1= Master ready. 0 = Master not ready.
AXI4 Interface Read Data Channel: Information Signals Derived from FIFO Data Input (din) Bus
m_axi_rid[m:0]	Input	Read ID Tag: ID tag of the read data group of signals. The RID value is generated by the slave and must match the ARID value of the read transaction to which it is responding.
m_axi_rdata[m-1:0]	Input	Read Data: Can be 8, 16, 32, 64, 128, 256 or 512 bits wide.
m_axi_ rresp[1:0]	Input	Read Response: Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
m_axi_rlast	Input	Read Last: Indicates the last transfer in a read burst.
m_axi_ruser[m:0]	Input	Read Data Channel User
AXI4 Interface Read Data Channel: Handshake Signals for FIFO Write Interface
m_axi_rvalid	Input	Read Valid: Indicates that the required read data is available and the read transfer can complete: 1 = Read data available. 0 = Read data not available.
m_axi_rready	Output	Read Ready: Indicates that the master can accept the read data and response information: 1= Master ready. 0 = Master not ready.
AXI4 Read Data Channel FIFO: Optional Sideband Signals
injectsbiterr_rdch	Input	Injects a single bit error if the ECC feature is used.
injectdbiterr_rdch	Input	Injects a double bit error if the ECC feature is used.
sbiterr_rdch	Output	Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error.
dbiterr_rdch	Output	Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.
wr_data_count_rdch[d:0]	Output	Write Data Count: This bus indicates the number of words written into the FIFO. The count is guaranteed to never underreport the number of words in the FIFO, to ensure you never overflow the FIFO. The exception to this behavior is when a write operation occurs at the rising edge of write clock, that write operation will only be reflected on wr_data_count at the next rising clock edge. D = log₂(FIFO depth)+1
rd_data_count_rdch[d:0]	Output	Read Data Count: This bus indicates the number of words available for reading in the FIFO. The count is guaranteed to never over-report the number of words available for reading, to ensure that you do not underflow the FIFO. The exception to this behavior is when the read operation occurs at the rising edge of read clock, that read operation is only reflected on rd_data_count at the next rising clock edge. D = log₂(FIFO depth)+1
prog_full_rdch	Output	Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable threshold. It is deasserted when the number of words in the FIFO is less than the programmable threshold.
prog_empty_rdch	Output	Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable threshold. It is deasserted when the number of words in the FIFO exceeds the programmable threshold.

AXI4-Lite FIFO Interface Signals

Write Channels

The following table defines the AXI4-Lite FIFO interface signals for the Write Address Channel.

Table 8. AXI4-Lite Write Address Channel FIFO Interface Signals
Name	Direction	Description
AXI4-Lite Interface Write Address Channel: Information Signals Mapped to FIFO Data Input (din) Bus
s_axi_awaddr[m:0]	Input	Write Address: Gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
s_axi_awprot[3:0]	Input	Protection Type: Indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
AXI4-Lite Interface Write Address Channel: Handshake Signals for FIFO Write Interface
s_axi_awvalid	Input	Write Address Valid: Indicates that valid write address and control information are available: 1 = Address and control information available. 0 = Address and control information not available. The address and control information remain stable until the address acknowledge signal, AWREADY, goes high.
s_axi_awready	Output	Write Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready. 0 = Slave not ready.
AXI4-Lite Interface Write Address Channel: Information Signals Derived from FIFO Data Output (dout) Bus
m_axi_awaddr[m:0]	Output	Write Address: Gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
m_axi_awprot[3:0]	Output	Protection Type: This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
AXI4-Lite Interface Write Address Channel: Handshake Signals for FIFO Read Interface
m_axi_awvalid	Output	Write Address Valid: Indicates that valid write address and control information are available: 1 = Address and control information available. 0 = Address and control information not available. The address and control information remain stable until the address acknowledge signal, AWREADY, goes high.
m_axi_awready	Input	Write Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready. 0 = Slave not ready.

The following table defines the AXI4-Lite FIFO interface signals for the Write Data Channel.

Table 9. AXI4-Lite Write Data Channel FIFO Interface Signals
Name	Direction	Description
AXI4-Lite Interface Write Data Channel: Information Signals Mapped to FIFO Data Input (din) Bus
s_axi_wdata[m-1:0]	Input	Write Data: Can be 8, 16, 32, 64, 128, 256 or 512 bits wide.
s_axi_wstrb[m/8-1:0]	Input	Write Strobes: Indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus. Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)]. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b, DATA[63:56] is not valid
AXI4-Lite Interface Write Data Channel: Handshake Signals for FIFO Write Interface
s_axi_wvalid	Input	Write Valid: Indicates that valid write data and strobes are available: 1 = Write data and strobes available. 0 = Write data and strobes not available.
s_axi_wready	Output	Write Ready: Indicates that the slave can accept the write data: 1 = Slave ready. 0 = Slave not ready.
AXI4-Lite Interface Write Data Channel: Information Signals Derived from FIFO Data Output (dout) Bus
m_axi_wdata[m-1:0]	Output	Write Data: Can be 8, 16, 32, 64, 128, 256 or 512 bits wide.
m_axi_wstrb[m/8-1:0]	Output	Write Strobes: Indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus. Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)]. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b, DATA[63:56] is not valid
AXI4-Lite Interface Write Data Channel: Handshake Signals for FIFO Read Interface
m_axi_wvalid	Output	Write Valid: Indicates that valid write data and strobes are available: 1 = Write data and strobes available 0 = Write data and strobes not available
m_axi_wready	Input	Write Ready: Indicates that the slave can accept the write data: 1 = Slave ready. 0 = Slave not ready.
AXI4-Lite Write Data Channel FIFO: Optional Sideband Signals
injectsbiterr_wdch	Input	Injects a single bit error if the ECC feature is used.
injectdbiterr_wdch	Input	Injects a double bit error if the ECC feature is used.
sbiterr_wdch	Output	Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error.
dbiterr_wdch	Output	Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.
wr_data_count_wdch[d:0]	Output	Write Data Count: This bus indicates the number of words written into the FIFO. The count is guaranteed to never underreport the number of words in the FIFO, to ensure you never overflow the FIFO. The exception to this behavior is when a write operation occurs at the rising edge of write clock, that write operation will only be reflected on wr_data_count at the next rising clock edge. D = log₂(FIFO depth)+1.
rd_data_count_wdch[d:0]	Output	Read Data Count: This bus indicates the number of words available for reading in the FIFO. The count is guaranteed to never over-report the number of words available for reading, to ensure that you do not underflow the FIFO. The exception to this behavior is when the read operation occurs at the rising edge of read clock, that read operation is only reflected on rd_data_count at the next rising clock edge. D = log₂(FIFO depth)+1.
prog_full_wdch	Output	Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable threshold. It is deasserted when the number of words in the FIFO is less than the programmable threshold.
w_prog_empty_wdch	Output	Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable threshold. It is deasserted when the number of words in the FIFO exceeds the programmable threshold.

The following table defines the AXI4-Lite FIFO interface signals for the Write Response Channel.

Table 10. AXI4-Lite Write Response Channel FIFO Interface Signals
Name	Direction	Description
AXI4-Lite Interface Write Response Channel: Information Signals Mapped to FIFO Data Output (dout) Bus
s_axi_bresp[1:0]	Output	Write Response: Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
AXI4-Lite Interface Write Response Channel: Handshake Signals for FIFO Read Interface
s_axi_bvalid	Output	Write Response Valid: Indicates that a valid write response is available: 1 = Write response available. 0 = Write response not available.
s_axi_bready	Input	Response Ready: Indicates that the master can accept the response information. 1 = Master ready. 0 = Master not ready.
AXI4-Lite Interface Write Response Channel: Information Signals Derived from FIFO Data Input (din) Bus
m_axi_bresp[1:0]	Input	Write response: Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
AXI4-Lite Interface Write Response Channel: Handshake Signals for FIFO Write Interface
m_axi_bvalid	Input	Write response valid: Indicates that a valid write response is available: 1 = Write response available. 0 = Write response not available.
m_axi_bready	Output	Response ready: Indicates that the master can accept the response information. 1 = Master ready. 0 = Master not ready.

Read Channels

The following table defines the AXI4-Lite FIFO interface signals for the Read Address Channel.

Table 11. AXI4-Lite Read Address Channel FIFO Interface Signals
Name	Direction	Description
AXI4-Lite Interface Read Address Channel: Information Signals Mapped to FIFO Data Input (din) Bus
s_axi_araddr[m:0]	Input	Read Address: The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
s_axi_arprot[3:0]	Input	Protection Type: This signal provides protection unit information for the transaction.
AXI4-Lite Interface Read Address Channel: Handshake Signals for FIFO Write Interface
s_axi_arvalid	Input	Read Address Valid: When high, indicates that the read address and control information is valid and will remain stable until the address acknowledge signal, arready, is High. 1 = Address and control information valid. 0 = Address and control information not valid.
s_axi_arready	Output	Read Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready. 0 = Slave not ready.
AXI4-Lite Interface Read Address Channel: Information Signals Derived from FIFO Data Output (dout) Bus
m_axi_araddr[m:0]	Output	Read Address: The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
m_axi_arprot[3:0]	Output	Protection Type: This signal provides protection unit information for the transaction.
AXI4-Lite Interface Read Address Channel: Handshake Signals for FIFO Read Interface
m_axi_arvalid	Output	Read Address Valid: When high, indicates that the read address and control information is valid and will remain stable until the address acknowledge signal, arready, is high. 1 = Address and control information valid. 0 = Address and control information not valid.
m_axi_arready	Input	Read Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready. 0 = Slave not ready.

The following table defines the AXI4-Lite FIFO interface signals for the Write Data Channel.

Table 12. AXI4-Lite Read Data Channel FIFO Interface Signals
Name	Direction	Description
AXI4-Lite Interface Read Data Channel: Information Signals Mapped to FIFO Data Output (dout) Bus
s_axi_rdata[m-1:0]	Output	Read Data: The read data bus can be 8, 16, 32, 64, 128, 256 or 512 bits wide.
s_axi_rresp[1:0]	Output	Read Response: Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
AXI4-Lite Interface Read Data Channel: Handshake Signals for FIFO Read Interface
s_axi_rvalid	Output	Read Valid: Indicates that the required read data is available and the read transfer can complete: 1 = Read data available. 0 = Read data not available.
s_axi_rready	Input	Read Ready: indicates that the master can accept the read data and response information: 1= Master ready. 0 = Master not ready.
AXI4-Lite Interface Read Data Channel: Information Signals Derived from FIFO Data Input (din) Bus
m_axi_rdata[m-1:0]	Input	Read Data: The read data bus can be 8, 16, 32, 64, 128, 256 or 512 bits wide.
m_axi_ rresp[1:0]	Input	Read Response: Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
AXI4-Lite Interface Read Data Channel: Handshake Signals for FIFO Write Interface
m_axi_rvalid	Input	Read Valid: Indicates that the required read data is available and the read transfer can complete: 1 = Read data available. 0 = Read data not available.
m_axi_rready	Output	Read ready: Indicates that the master can accept the read data and response information: 1= Master ready. 0 = Master not ready.
AXI4-Lite Read Data Channel FIFO: Optional Sideband Signals
injectsbiterr_rdch	Input	Inject Single-Bit Error: Injects a single bit error if the ECC feature is used.
injectdbiterr_rdch	Input	Inject DOuble-Bit Error. Injects a double bit error if the ECC feature is used.
sbiterr_rdch	Output	Single-Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error.
dbiterr_rdch	Output	Double-Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.
wr_data_count_rdch[d:0]	Output	Write Data Count: This bus indicates the number of words written into the FIFO. The count is guaranteed to never underreport the number of words in the FIFO, to ensure you never overflow the FIFO. The exception to this behavior is when a write operation occurs at the rising edge of write clock, that write operation will only be reflected on wr_data_count at the next rising clock edge. D = log₂(FIFO depth)+1.
rd_data_count_rdch[d:0]	Output	Read Data Count: This bus indicates the number of words available for reading in the FIFO. The count is guaranteed to never over-report the number of words available for reading, to ensure that you do not underflow the FIFO. The exception to this behavior is when the read operation occurs at the rising edge of read clock, that read operation is only reflected on rd_data_count at the next rising clock edge. D = log₂(FIFO depth)+1.
prog_full_rdch	Output	Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable threshold. It is deasserted when the number of words in the FIFO is less than the programmable threshold.
prog_empty_rdch	Output	Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable threshold. It is deasserted when the number of words in the FIFO exceeds the programmable threshold.

AXI FIFO Interface Signals - 1.0 English

Embedded FIFO Generator LogiCORE IP Product Guide (PG327)

Global Signals

AXI4-Stream FIFO Interface Signals

AXI4 FIFO Interface Signals

Read Channels

AXI4-Lite FIFO Interface Signals

Read Channels