AXI Interface FIFOs - 1.0 English

Embedded FIFO Generator LogiCORE IP Product Guide (PG327)

Document ID
PG327
Release Date
2023-05-10
Version
1.0 English

AXI interface FIFOs are derived from the Native interface FIFO, as shown in the following figure. Three AXI interface styles are available: AXI4-Stream, AXI4, and AXI4-Lite. In addition to applications supported by the Native interface FIFO, AXI FIFOs can also be used in AXI System Bus and Point-to-Point high speed applications.

Use the AXI FIFOs in the same applications supported by the Native Interface FIFO when you need to connect to other AXI functions. AXI FIFOs can be integrated into a system by using the IP integrator. See the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for more details.

Figure 1. AXI FIFO Derivation

The AXI interface protocol uses a two-way valid and ready handshake mechanism. The information source uses the valid signal to show when valid data or control information is available on the channel. The information destination uses the ready signal to show when it can accept the data. The following figures show an example timing diagram for write and read operations to the AXI4-Stream FIFO, and an example timing diagram for write and read operations to the AXI memory mapped interface FIFO.

Figure 2. AXI4-Stream FIFO Timing
Figure 3. AXI Memory Mapped Interface FIFO Timing

The information source generates the valid signal to indicate when the data is available. The destination generates the ready signal to indicate that it can accept the data, and transfer occurs only when both the valid and ready signals are High.

Because AXI FIFOs are derived from Native interface FIFOs, much of the behavior is common between them. The ready signal is generated based on availability of space in the FIFO and is held high to allow writes to the FIFO. The ready signal is pulled Low only when there is no space in the FIFO left to perform additional writes. The valid signal is generated based on availability of data in the FIFO and is held High to allow reads to be performed from the FIFO. The valid signal is pulled Low only when there is no data available to be read from the FIFO. The information signals are mapped to the din and dout bus of Native interface FIFOs. The width of the AXI FIFO is determined by concatenating all of the information signals of the AXI interface. The information signals include all AXI signals except for the valid and ready handshake signals.

AXI FIFOs operate only in First-Word Fall-Through mode. The First-Word Fall-Through (FWFT) feature provides the ability to look ahead to the next word available from the FIFO without issuing a read operation. When data is available in the FIFO, the first word falls through the FIFO and appears automatically on the output data bus.