Basic Options Tab - 1.0 English

Embedded FIFO Generator LogiCORE IP Product Guide (PG327)

Document ID
PG327
Release Date
2023-05-16
Version
1.0 English

The Basic Options Tab defines the component name and required essential options for the core.

Figure 1. Basic Options Tab
Component Name
Base name of the output files generated for this core. The name must begin with a letter and be composed of the following characters: a to z, 0 to 9, and "_".
Interface Type
  • Native: Implements a Native FIFO.
  • AXI Full/Lite: Implements an AXI4, and AXI4-Lite FIFOs in First-Word-Fall-Through mode.
  • AXI Stream: Implements an AXI4-Stream FIFO in First-Word-Fall-Through mode.
Clocking Options
  • Common Clock: Implements the FIFO using single wr_clk clock
  • Independent Clock: Implements the FIFO using two clocks, wr_clk for write domain and rd_clk for read domain
FIFO Memory Type
  • AUTO: Lets AMD Vivado™ Synthesis to pick the memory type to build the FIFO
  • Block RAM: Implements the FIFO using block RAM
  • LUTRAM: Implements the FIFO using distributed RAM
  • UltraRAM: Implements the FIFO using UltraRAM
Cascade Height
  • This parameter specifies the number of Block RAMs/UltraRAMs will be there in one cascade chain.
  • To implement a memory that requires more than 1 Block RAM/UltraRAM, it need to connect several Block RAMs/UltraRAMs using built-in cascade and/or fabric LUTs (muxes).
  • When cascade_height = 1, synthesis uses NO cascade at all. This is used for maximum timing performance.
  • XPM uses default value of 0 which is similar to no specification in cascade_height, so synthesis has an option to choose cascading or not.
Synchronization stages
Defines the number of synchronizers stages across the cross clock domain logic. This option is available if the Clocking Options is set to Independent Clock.
Related Clock
Available only for Independent Clock FIFOs. Defines if wr_clk rd_clk are derived from same clock source having the frequency relationship in integer multiples.
Read Mode
  • Standard FIFO: Implements a FIFO with standard latencies and without using output registers. and
  • First-Word Fall-Through FIFO: Implements a FIFO with registered outputs.
FIFO Read Latency
Implements FIFO with configurable read latencies. Available only for Standard FIFO implementation.
Data Port Parameters
  • Write Width: The valid range of write data width is 1 to 4096.
  • Write Depth: The valid range of write depth is 16 to 4194304. Only depths with powers of 2 are allowed.
  • Read Width: Available only if FIFO Memory Type is block RAM or UltraRAM.
ECC Options
  • ECC: When the Error Correction Checking (ECC) feature is enabled, the block RAM or UltraRAM FIFO is set to the full ECC mode, where both the encoder and decoder are enabled.
  • Single Bit Error Injection: Generates an input port to inject a single bit error on write and an output port that indicates a single bit error occurred.
  • Double-Bit Error Injection: Generates an input port to inject a double-bit error on write and an output port that indicates a double-bit error occurred.
Reset Options
  • Full Flags Reset Value: Defines the reset value of the full flags (prog_full, almost_full, and full) during reset.
  • Dout Reset Value: Indicates the hexadecimal value asserted on the output of the FIFO when the reset is asserted. If selected, the dout output of the FIFO will reset to the defined dout Reset Value when the reset is asserted. If not selected, the dout output of the FIFO will not be effected by the assertion of reset, and dout will hold its previous value.