Built-in Error Injection is supported for FIFOs configured with block RAM and
UltraRAM FIFOs. When ECC and Error Injection are enabled, the block RAM and UltraRAM
primitive used to create the FIFO is configured in the full ECC error injection mode,
providing two additional inputs to the Embedded FIFO Generator
core: injectsbiterr and injectdbiterr. These inputs indicate four possible results: no error
injection, single bit error injection, double bit error injection, or both single bit
and double bit error injection.
The ECC is calculated on a 64-bit wide data of ECC primitives. If the data width
chosen is not an integral multiple of 64 (for example, there are spare bits in any ECC
primitive), then a double bit error (dbiterr) can
indicate that one or more errors have occurred in the spare bits. In this case, the
accuracy of the dbiterr signal cannot be guaranteed. For
example, if the data width is set to 16, then 48 bits of the ECC primitive are left
empty. If two of the spare bits are corrupted, the dbiterr signal would be asserted even though the actual user data is not
corrupt.
When injectsbiterr is asserted on a Write
operation, a single bit error is injected and sbiterr
is asserted upon read operation of a specific write. When injectdbiterr is asserted on a Write operation, a double bit error is
injected and dbiterr is asserted upon read operation of
a specific write. When both injectsbiterr and injectdbiterr are asserted on a write operation, a double
bit error is injected and dbiterr is asserted upon read
operation of a specific write. The following figure shows how the sbiterr and dbiterr
outputs are generated in the Embedded FIFO Generator core.
Reset is not supported by the UltraRAM/block RAM macros when using the ECC
option. Therefore, outputs of the FIFO core (dout,
dbiterr and sbiterr) are not affected by reset, and they hold their previous values.
See Resets for more details.
