The Embedded FIFO Generator is designed to work only
with free-running write and read clocks. AMD does
not recommend controlling the core by manipulating rd_clk and wr_clk. If this functionality
is required to gate FIFO operation, AMD recommends using the
write enable (wr_en) and read enable (rd_en) signals.
If the clock(s) is/are lost during the normal operation, use
BUFGCE to make the clock line flat to ensure that the Embedded FIFO Generator core is not operating on a perturbed clock.
It is highly recommended to release the reset only when the clock(s) is/are stable.