The block RAM macros and UltraRAM macros have built-in embedded registers that
can be used to pipeline data and improve macro timing. The Embedded FIFO Generator provides an option to select configurable read latency
feature. The chosen Read Mode decides the latency added at the output (dout). Depending
on the configuration, this feature can be leveraged to add an additional latency to the
FIFO core (dout bus and valid outputs) or implement the
output registers for FWFT FIFOs.
Standard FIFOs
When using the FIFO Read Latency option to add an output register to the
standard FIFOs, only the dout and VALID output ports are delayed by FIFO Read Latency clock
cycle during a read operation. These additional pipeline registers are always
enabled.
FWFT FIFOs
When using the FWFT FIFOs, the behavior of the core is identical to the implementation without any read latency. The FIFO Read Latency option is not applicable.
The empty gives a latency of one more cycle as compared to selecting only one register, before rd_en signal is initiated. The next output is latched when rd_en initiates without any additional latency for block RAM as shown in the following figure.
