- Supports Native, AXI4-Stream, AXI4, and AXI4-Lite interfaces.
- FIFO depths up to 4194304 or 2^22 entries.
- Independent or common clock domains.
- Fully configurable using the AMD Vivado™ Design Suite IP catalog.
Native FIFO Specific Features
- FIFO data widths from 1 to 4096 bits.
- Symmetric or Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1).
- Synchronous reset option.
- Selectable memory type (block/UltraRAM and distributed RAM).
- Option to operate in Standard or first-word fall-through modes (FWFT).
- Full and Empty status flags, and Almost Full and Almost Empty flags for indicating one-word-left.
- Programmable Full and Empty status flags, set by user-defined constant(s).
- Hamming error injection and correction checking (ECC) support for block RAM and UltraRAM FIFO configurations.
- Configurable read latency for Standard Read Mode.
- Dynamic Power Gating.
AXI FIFO Features
- FIFO data widths:
- AXI4-Stream: 1 to 4096 bits
- AXI4: 32, 64....... 1024 (multiples of 2) bits
- AXI4-Lite: 32, 64 bits
- Supports AXI4 memory mapped, AXI4-Stream, and AXI4-Lite.
- Symmetric aspect ratios.
- Asynchronous active-Low reset.
- Selectable memory type (block/UltraRAM, or distributed RAM).
- Selectable application type (Data FIFO and Packet FIFO).
- Packet FIFO feature is available only for common/independent clock AXI4-Stream FIFO and common clock AXI4 FIFOs.
- Operates in first-word fall-through mode (FWFT).
- Auto-calculation of FIFO width based on AXI signal selections and data and address widths.
- Hamming error injection and correction checking (ECC) support for block / UltraRAM FIFO configurations.
- Configurable programmable Full/Empty flags as sideband signals.