The following figure illustrates the functional implementation of a FIFO configured with independent clocks. This implementation uses block RAM or Distributed RAM for memory, counters for write and read pointers, conversions between binary and Gray code for synchronization across clock domains, and logic for calculating the status flags.
This FIFO is designed to support an independent read clock (rd_clk) and write
clock (wr_clk); in other words, there is no required relationship between
rd_clk and wr_clk with regard to frequency or phase. The following
table summarizes the FIFO interface signals, which are only valid in their respective
clock domains.
| wr_clk | rd_clk |
|---|---|
| din | dout |
| wr_en | rd_en |
| full | empty |
| almost_full | almost_empty |
| prog_full | prog_empty |
| wr_ack | data_valid |
| overflow | underflow |
| wr_data_count | rd_data_count |
| wr_rst | rd_rst |
| injectsbiterr | sbiterr |
| injectdbiterr | dbiterr |
For FIFO cores using independent clocks, the timing relationship between the write and
read operations and the status flags is affected by the relationship of the two clocks.
For example, the timing between writing to an empty FIFO and the deassertion of
empty is determined by the phase and frequency relationship between the
write and read clocks.