The AMD LogiCORE™ IP Embedded FIFO Generator core is a fully verified first-in first-out (FIFO) memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while utilizing minimum resources. Delivered through the AMD Vivado™ Design Suite, you can customize the width, depth, status flags, memory type, and the write/read port aspect ratios.
The Embedded FIFO Generator core supports Native interface FIFOs, AXI Memory Mapped interface FIFOs and AXI4-Stream interface FIFOs. Native interface FIFO cores are optimized for buffering, data width conversion and clock domain decoupling applications, providing ordered storage and retrieval.
AXI Memory Mapped and AXI4-Stream interface FIFOs are derived from the Native interface FIFO. Two AXI Memory Mapped interface styles are available: AXI4 and AXI4-Lite.