This section defines the latency in which different output signals of the FIFO
are updated in response to read or write operations.
Note: Latency is defined as the number of
clock edges after a read or write operation occurs before the signal is updated. For
example, if latency is 0, that means that the signal is updated at the clock edge in which
the operation occurred. This is shown in the following figure in which
wr_ack is getting updated when wr_en is High.Figure 1. Latency 0 Timing
