In digital designs, FIFOs are ubiquitous constructs required for data
manipulation tasks such as clock domain crossing, low-latency memory buffering, and bus
width conversion. The following figure highlights just one of many configurations that
the Embedded FIFO Generator core supports. In this example, the
design has two independent clock domains and the width of the write data bus is four
times wider than the read data bus. Using the Embedded FIFO Generator core, you are able to rapidly generate solutions such as
this one, that is customized for their specific requirements and provides a solution
fully optimized for AMD devices.
Figure 1.
Embedded FIFO Generator core
Application Example
