Clock Implementation and Operation
The Embedded FIFO Generator core enables FIFOs to be configured with either independent or common clock domains for write and read operations. The independent clock configuration of the Embedded FIFO Generator core enables you to implement unique clock domains on the write and read ports. The Embedded FIFO Generator core handles the synchronization between clock domains, placing no requirements on phase and frequency. When data buffering in a single clock domain is required, the Embedded FIFO Generator core can be used to generate a core optimized for that single clock.
First-Word Fall-Through (FWFT)
The first-word fall-through (FWFT) feature provides the ability to look-ahead to the next word available from the FIFO without issuing a read operation. When data is available in the FIFO, the first word falls through the FIFO and appears automatically on the output bus (dout). FWFT is useful in applications that require Low-latency access to data and to applications that require throttling based on the contents of the read data. FWFT support is included in FIFOs created with block RAM, Distributed RAM, or UltraRAM.
See the FIFO Configurations table for FWFT availability. The use of this feature impacts the behavior of many other features, such as:
- Read operations
- Programmable empty
- Data counts
Supported Memory Types
The Embedded FIFO Generator core implements FIFOs built from block RAM, Distributed RAM, or UltraRAM. The following table provides best-use recommendations for specific design requirements.
| Memory Types | Independent Clocks | Common Clock | Small Buffering | Medium - Large Buffering | High Performance | Minimal Resources |
|---|---|---|---|---|---|---|
| Block RAM | ✓ | ✓ | ✓ | ✓ | ✓ | |
| UltraRAM | ✓ | ✓ | ✓ | ✓ | ||
| Distributed RAM | ✓ | ✓ | ✓ | ✓ |
Non-Symmetric Aspect Ratio Support
The core supports generating FIFOs with write and read ports of different widths, enabling automatic width conversion of the data width. Non-symmetric aspect ratios ranging from 1:8 to 8:1 are supported for the write and read port widths. This feature is available for the following FIFO implementations:
- Common or Independent clock block RAM FIFOs
- Common clock UltraRAM FIFOs
Configurable Read Latency
The core supports configurable read latency, ranging from 1 to 16 for Standard Read Mode FIFOs. For FWFT FIFOs, the supported latency is 0.
Error Injection and Correction (ECC) Support
The block RAMs and UltraRAMs are equipped with built-in Error Injection and Correction Checking. This feature is available for Common/Independent Clock block RAM FIFOs and Common Clock UltraRAM FIFOs.