Performance for a Native interface FIFO varies depending on the configuration and features selected during core customization.
The benchmarks were performed while adding two levels of registers on all
inputs (except clock) and outputs having only the period constraints in the XDC. To
achieve the performance shown in the following tables, ensure that all inputs to the
FIFO are registered and that the outputs are not passed through many logic
levels.
Tip: The Distributed Memory FIFO is more suitable in terms of resource and
performance if the depth of the FIFO is around 16 or 32.