When independent clock domains are selected, the full flag (full, almost_full) and empty flag (empty, almost_empty) are pessimistic flags. The full and almost_full flags are synchronous
to the write clock (wr_clk) domain, while empty and almost_empty are
synchronous to the read clock (rd_clk) domain.
The full flags are considered pessimistic flags because they assume that no
read operations have taken place in the read clock domain. The almost_full flag is guaranteed to be asserted on the rising edge of
wr_clk when there is only one available location in
the FIFO, and full is guaranteed to be asserted on the
rising edge of wr_clk when the FIFO is full. There can
be a number of clock cycles between a read operation and the deassertion of full. The precise number of clock cycles for full to deassert is not predictable due to the crossing of
clock domains and synchronization logic.
The empty flags are considered pessimistic
flags because they assume that no write operations have taken place in the write clock
domain. The almost_empty flag is guaranteed to be
asserted on the rising edge of rd_clk when there is
only one more word in the FIFO, and empty is guaranteed
to be asserted on the rising edge of rd_clk when the
FIFO is empty. There can be a number of clock cycles between a write operation and the
deassertion of empty. The precise number of clock
cycles for empty to deassert is not predictable due to the crossing of clock domains and
synchronization logic.