The Embedded FIFO Generator core provides a reset
input that resets all counters and output registers when asserted. The readiness of FIFO is
indicated by wr_rst_busy, transition from 1 to 0. The synchronous reset (
rst) input is synchronous to wr_clk
and synchronously resets all counters, output registers, and memories when asserted. For
independent clock FIFOs, the reset is synchronized internally to the core with each respective
clock domain for setting the internal logic of the FIFO to a known state. This synchronization
logic allows for proper timing of the reset logic within the core to avoid glitches and
metastable behavior.Important: The clock(s) must be available when the reset is applied. If for any
reason, the clock(s) is/are lost at the time of reset, you must release the reset only when
the clock(s) is/are available. Violating this requirement might cause an unexpected
behavior. Sometimes, the busy signals might be stuck and need reconfiguration of the
FPGA.
Note: Because the
reset is synchronous to
wr_clk, the reset can be as small
as one wr_clk duration.Figure 1. Reset Behavior with Common Clock FIFOs
Note: All FIFO outputs during No Access
Zone should be considered as invalid.
Figure 2. Reset Behavior with Independent Clock FIFOs
Note: All FIFO outputs during No Access
Zone should be considered as invalid.
The following table defines the values of the output ports during power-up
and reset state. Note that the underflow signal is dependent on rd_en. If rd_en is asserted and the FIFO is
empty, underflow is asserted. The overflow signal is dependent on wr_en. If wr_en is asserted and the FIFO is full,
overflow is asserted.
| Signal | Full Flags Reset Value of 1 | Full Flags Reset Value of 0 | Power-up Values |
|---|---|---|---|
| dout | dout Reset Value or 0 | dout Reset Value or 0 | Same as reset values |
| full | 1 1 | 0 | 0 |
| almost full | 1 1 | 0 | 0 |
| empty | 1 | 1 | 1 |
| almost empty | 1 | 1 | 1 |
| data_valid | 0 | 0 | 0 |
| wr_ack | 0 | 0 | 0 |
| prog_full | 1 1 | 0 | 0 |
| prog_empty | 1 | 1 | 1 |
| rd_data_count | 0 | 0 | 0 |
| wr_data_count | 0 | 0 | 0 |
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