NVMe Host Accelerator LogiCORE IP Product Guide (PG328) - 1.0 English

Document ID: PG328
Release Date: 2023-05-16
Version: 1.0 English

Introduction
Features
IP Facts
Overview
Core Overview
Licensing and Ordering
License Checkers
Product Specification
Performance and Resource Use
Port Descriptions
AXI4-Lite Interface Ports
SW AXI Interface Ports
HW AXI Interface Ports
SSD Master AXI Interface Ports for Doorbell Rings
SSD Slave AXI Interface Ports for SQ Reads and CQ Writes
Interrupts
Register Space
SSDn PCIe Base Address Lower Register (0x0000 + (n * 8))
SSDn PCIe Base Address Upper Register (0x0004 + (n * 8))
SSD0 SQ1 Base Address Register (0x0100)
SSD0 CQ1 Base Address Register (0x0104)
SSDn SQm Base Address Register (0x0100 + (m * C_MAX_SQ * 16) + (n * 16))
SSDn CQm Base Address Register (0x0104 + (m * C_MAX_SQ * 16) + (n * 16))
SSDn SQm Flush Register (0x0108 + (m * C_MAX_SQ * 16) + (n * 16))
SSDn SQm Flush Done Status Register (0x010C + (m * C_MAX_SQ * 16) + (n * 16))
Interrupt Enable Register (0x8104)
Interrupt Status Register (0x8108)
CQ Available Count Register (0x810C)
Command Error Count Register (0x8110)
Timeout Register (0x8114)
SSDn Issued Commands Count Register (0x8200 + (n * 16))
SSDn Error Completion Commands Count Register (0x8204 + (n * 16))
SSDn Completion Commands Count Register (0x8208 + (n * 16))
SSDn/SQmCQm Status Register (0x8400 + (n * C_MAX_SQ *4) + (m * 4))
Designing with the Core
General Design Guidelines
Use the Example Design
Registering Signals
Recognize Timing Critical Signals
Make Only Allowed Modifications
Reference Design
Design Flow Steps
Customizing and Generating the Core
User Parameters
Output Generation
NVMe Host Accelerator Programming Sequence
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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