Revision History - 3.0 English

NVMe Target Controller LogiCORE IP Product Guide (PG329)

Document ID
Release Date
3.0 English

The following table shows the revision history for this document.

Section Revision Summary
10/27/2021Version 3.0
QDMA FLR Port and User Interrupt Port Updated the table in the section
Navigating Content by Design Process Added a new section to the document.
Interfacing NVMe Target Controller IP with Versal ACAP CPM DMA and Bridge Mode for PCI Express configured in QDMA Mode Added a new section to the document.
Interface Ports Associated with QDMA Added tables for C_CPM_QDMA = 1 parameter in the sub-sections of this section.
12/04/2020 Version 2.0
Port Descriptions Updated
QDMA Register Access (C_CPM_QDMA = 0) Added
06/03/2020 Version 1.0
Initial release. N/A