Work Queue Manager - 3.0 English

NVMe Target Controller LogiCORE IP Product Guide (PG329)

Document ID
Release Date
3.0 English

This module manages the data movement between card to host and host to card and is also responsible for posting completions. This module receives the work instructions/requests also referred to as work queue entries (WQE) from the software application/hardware module and programs the QDMA for the required data transfer. The hardware application pushes these WQEs through the wqe_s_axis interface. Internally, the IP maintains two FIFOs for incoming WQEs. All WQEs that transfer data from the host to FPGA (H2C) are pushed to H2C FIFO while all WQEs that transfer data from FPGA to the host (C2H) are pushed to the C2H FIFO. Two FIFO full signals (h2c_wqe_fifo_full and c2h_wqe_fifo_full) are also provided to the hardware applications. The application is expected to not push WQEs for the respective data transfers if the corresponding fifo_full bits are set. The NVMe TC IP drops any packets targeted to FIFOs that are full and sets the appropriate status register bits in DBG_WQE_MGR register. The WQEs are temporarily stored in these FIFOs until they are processed and pushed to the relevant QDMA queues. The same structure of WQEs is also applicable to the software interface.

The structure of the WQE is given in the following table:

Table 1. Work Queue Entry Format
Bitwidth Field Size (Bytes) Comment
[15:0] WRID 2 Work Request ID. Unique Identifier for every WQE
[31:16] SQID 2 Submission Queue ID
[47:32] FNID 2 Function ID=0
[55:48] OPCODE 1 8’h00 = C2H DMA Descriptor (Push only when c2h_wqe_fifo_full is 0)

8’h02 = NVMe H2C/C2H Completion 1

8’h03 = NVMe H2C Completion 1 (Optional)

8’h04 = H2C DMA Descriptor (Push Only when h2c_wqe_fifo_full is 0)

Note: All other OPCODEs are reserved.
[63:56] RESERVED 1 Reserved
[127:64] LADDR/CQE_LSB 8 Local Buffer Address for DMA (or)

CQE {DW1, DW0} for NVMe Completion

Note: Local Buffer Address must be 4 KB aligned.
[191:128] HADDR/CQE_MSB 8 Host Buffer Address for DMA (or)

CQE {DW3, DW2} for NVMe Completion

[207:192] LENGTH 2 Data transfer length for DMA’s

Reserved if (OPCODE = 8’h02 or 8’h03)

[223:208] UID 2 UID of the command that is getting completed. Only valid if the (OPCODE = 8’h02 or 8’h03)
[255:224] Reserved 4 Reserved
  1. Push only when c2h_wqe_fifo_full is 0.
Note: The phase bit and HSQ head pointer information in the CQE is replaced by the NVMe TC IP.

If the work queue entry is posted to send the NVMe completion (CQE) information to the host, the completion data (CQE) can be inserted in the work request itself. Also, in this case the UID information in the work queue entry is used by the NVMe TC IP to free up the resources related to the corresponding command.