There are 4 clocking inputs possible, and each input has an associated synchronous reset. Ensure that the proper clock is connected to aud_mclk so that Audio samples are generated at the required sampling rate in case of MM2S. Audio clock is typically an integer multiple of required frequency sampling rate (Fs). It is best practice to use a very stable clock source to generate the Audio Clock to minimize jitter.
| Clock | Description |
|---|---|
| s_axi_lite_aclk | Used on AXI4-Lite interface for register reads and writes for both S2MM and MM2S. |
| m_axis_mm2s_aclk | Used for reading from memory as audio stream output. AXI4 MM2S Stream and AXI4 MM2S Memory mapped interface ports work on this clock. |
| s_axis_s2mm_aclk | Used to write audio stream input to memory. AXI4 S2MM Stream and AXI4 S2MM Memory mapped interface ports work on this clock. |
| aud_mclk | Used as a master reference clock to generate audio stream in case of MM2S at a required sampling rate. Typically a multiple of sampling rate frequency. |
All the signals are well synchronized to avoid CDC issues. In case of synchronous clocks for s_axi_lite_aclk and S2MM clock or MM2S clock, the corresponding ASYNC_CLOCKS parameter can be disabled to reduce to resource count.
When ASYNC_CLOCKS parameter is 0 and clocks are not synchronous, IP behavior is not guaranteed.