IP Facts - 1.0 English

Audio Formatter LogiCORE IP Product Guide (PG330)

Document ID
Release Date
1.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1



Zynq® UltraScale+™ MPSoC

7 series

Supported User Interfaces AXI4, AXI4-Lite, AXI4-Stream
Resources Performance and Resource Use web page
Provided with Core
Design Files Register Transfer Level (RTL)
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Constraints File
Simulation Model Not Provided
Supported S/W Driver 2 Standalone and Linux
Tested Design Flows 3
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado® synthesis
Release Notes and Known Issues Master Answer Record: 54489
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. Standalone driver information can be found in the Software Development Kit (SDK) (SDK) installation directory. See xilinx_drivers.htm in <install_directory>/SDK/<release>/data/embeddedsw/doc/xilinx_drivers.htm. Linux OS and driver support information is available on the Xilinx Wiki. For reference, see AXI DMA.
  3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.