| 31:23 |
0x0 |
- |
Reserved |
| 22:19 |
0x2 |
R/W |
Number of valid channels: Valid
values are 2,4,6,8. This value must be less than or equal to maximum no. of channels
programmed through GUI. |
| 18:16 |
0x2 |
R/W |
PCM data width: PCM data width of
data present in the memory.
- 0x0 : 8 bits
- 0x1 : 16 bits
- 0x2 : 20 bits
- 0x3 : 24 bits
- 0x4 : 32 bits (Complete AES)
|
| 15:14 |
- |
- |
Reserved |
| 13 |
0x1 |
R/W |
IOC_IrqEn: Enable interrupt on
complete (IOC).
- 1: Enables Interrupt after each period of data is
transferred
- 0: Disables interrupt
|
| 12 |
0x0 |
R/W |
Err_IrqEn: Enables interrupt on error. |
| 11:2 |
- |
- |
Reserved |
| 1 |
0x0 |
R/W |
Reset: Soft reset for resetting
the MM2S core. Setting this bit to a 1 causes the MM2S core to be reset. Reset is
accomplished gracefully. Pending commands/transfers are flushed or completed.
AXI4-Stream outs are terminated early. After completion of a
soft reset, all registers and bits are in the Reset State.
- 0 = Reset not in progress. Normal operation/Out of reset.
- 1 = Reset in progress.
|
| 0 |
0x0 |
R/W |
Run/Stop: Run/Stop control for
controlling running and stopping of the DMA channel.
- 0 = Stop – MM2S stops when current (if any) DMA operations are
complete. Pending commands/transfers are flushed or completed. AXI4-Streams are potentially terminated. The halt in process bit in
MM2S Status register shows the status of halt.
- 1 = Run – Start MM2S operations.
|