Register Space - 1.0 English

Audio Formatter LogiCORE IP Product Guide (PG330)

Document ID
PG330
Release Date
2020-07-08
Version
1.0 English

The Audio Formatter IP registers are memory-mapped into non-cacheable memory space. This memory space must be aligned on an AXI word (32-bit) boundary.

Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address Valid (*_awvalid) and the AXI Write Data Valid (*_wvalid) signals should be asserted together.
Table 1. Audio Formatter Register Address Space
Address (hex) Register
0x00 Core Version: Returns the core Major and Minor version
0x04 Core Configuration: Returns the core configuration details
0x10 S2MM Control: S2MM Control options
0x14 S2MM Status: Status of S2MM DMA transfer
0x18 S2MM Timeout: Timeout count value
0x1C S2MM Period Config: Register to program period size and no. of periods
0x20 S2MM Buffer Address LSB: Buffer Start Address LSB
0x24 S2MM Buffer Address MSB: Buffer Start Address MSB
0x28 S2MM Transfer Count: Count of data transferred to memory
0x2C – 0x40 S2MM Channel status bits: Read only Channel status bits
0x44 S2MM Channel Offset: Bytes per channel in a period
0x110 MM2S Control: MM2S Control Options
0x114 MM2S Status: Status of the MM2S DMA transfer
0x118 MM2S Fs Multiplier: Register to specify Fs multiplier
0x11C MM2S Period Config: Register to program period size and number of periods
0x120 MM2S Buffer Address LSB: Buffer Start Address LSB
0x124 MM2S Buffer Address MSB: Buffer Start Address MSB
0x128 MM2S Transfer Count: Count of data read from memory
0x12C – 0x140 AES Encode Channel Status: Channel Status Bits to Embed
0x144 MM2S Channel Offset: Bytes per channel in a period