S2MM Control Register (0x10) - 1.0 English

Audio Formatter LogiCORE IP Product Guide (PG330)

Document ID
Release Date
1.0 English
Bit Default Value Access Type Description
31:23 0x0 - Reserved
22:19 0x2 R/W Number of valid channels: Valid values are 2,4,6,8. This value must be less than or equal to maximum no. of channels programmed through GUI.
18:16 0x2 R/W PCM data width: PCM data width to write to memory.
  • 0x0: 8 bits
  • 0x1: 16 bits
  • 0x2: 20 bits
  • 0x3: 24 bits
  • 0x4: 32 bits (Complete AES)
15 - - Reserved
14 0x1 R/W Timeout_IrqEn: Enables interrupt on timeouts.
  • 1: Enables interrupt when timeout occurs
  • 0: Disables interrupt
13 0x1 R/W IOC_IrqEn: Enables interrupt on completion.
  • 1: Enables interrupt after each period size of data is transferred
  • 0: Disables interrupt
12 0x0 R/W Err_IrqEn: Enables interrupt on error.
11:2 - - Reserved
1 0x0 R/W Reset: Soft reset for resetting the S2MM core. Setting this bit to a 1 causes the S2MM part of the IP to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream outs are terminated early. After completion of a soft reset, all registers and bits are in the Reset State.
  • 0 = Reset not in progress. Normal operation. Out of reset.
  • 1 = Reset in progress.
0 0x0 R/W

Run/Stop control for controlling running and stopping of the S2MM channel.

  • 0 = Stop.

    S2MM part of the IP stops when current (if any) DMA operations are complete. Pending commands/transfers are flushed or completed. AXI4-Streams are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed. The halt_in_process bit (Bit 0) in S2MM Status register goes from 1 to 0 when the halt process is complete.

  • 1 = Run. Start S2MM operations.