|Bit||Default Value||Access Type||Description|
|22:19||0x2||R/W||Number of valid channels: Valid values are 2,4,6,8. This value must be less than or equal to maximum no. of channels programmed through GUI.|
PCM data width: PCM data width to
write to memory.
Timeout_IrqEn: Enables interrupt
IOC_IrqEn: Enables interrupt on
|12||0x0||R/W||Err_IrqEn: Enables interrupt on error.|
Reset: Soft reset for resetting
the S2MM core. Setting this bit to a 1 causes the S2MM part of the IP to be reset.
Reset is accomplished gracefully. Pending commands/transfers are flushed or
completed. AXI4-Stream outs are terminated early. After completion of a soft reset,
all registers and bits are in the Reset State.
Run/Stop control for controlling running and stopping of the S2MM channel.