Bit | Default Value | Access Type | Description |
---|---|---|---|
31:23 | 0x0 | - | Reserved |
22:19 | 0x2 | R/W | Number of valid channels: Valid values are 2,4,6,8. This value must be less than or equal to maximum no. of channels programmed through GUI. |
18:16 | 0x2 | R/W |
PCM data width: PCM data width to
write to memory.
|
15 | - | - | Reserved |
14 | 0x1 | R/W |
Timeout_IrqEn: Enables interrupt
on timeouts.
|
13 | 0x1 | R/W |
IOC_IrqEn: Enables interrupt on
completion.
|
12 | 0x0 | R/W | Err_IrqEn: Enables interrupt on error. |
11:2 | - | - | Reserved |
1 | 0x0 | R/W |
Reset: Soft reset for resetting
the S2MM core. Setting this bit to a 1 causes the S2MM part of the IP to be reset.
Reset is accomplished gracefully. Pending commands/transfers are flushed or
completed. AXI4-Stream outs are terminated early. After completion of a soft reset,
all registers and bits are in the Reset State.
|
0 | 0x0 | R/W |
Run/Stop control for controlling running and stopping of the S2MM channel.
|