Using the example design delivered as part of the Audio Formatter IP core, you can quickly simulate and observe the behavior of the core.
Setting Up the Simulation
The Xilinx® simulation libraries must be mapped to the simulator. The example design supports functional (behavioral) and post-synthesis simulations.
For comprehensive information about Vivado® simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900).
The simulation script compiles the example design and supporting simulation files. It then runs the simulation and checks that it completed successfully after simulating for 3ms, and displays either of the following messages:
Test Completed Successfully