GT Reference Clock Summary and Optimization - 1.1 English

As part of block automation, GT Reference Clocks (GTREFCLK) are shorted across GT Quads for simple designs. The GT Reference Clock summary reads the interface properties of GT Quad in the IP integrator and provides the summary of reference clock connections in the design.

Example 1

For an x8 design that uses two GT Quads, GTREFCLKs from both GT Quads are shorted and connected to a single IBUFDS_GT. For complex designs using Mulitple Bridge IPs with Multiple GT Quads, System designers can short or separate GTREFCLKs based on their frequency information, Quad placement, and Clock availability on the board. To help System designers to make an informed decision, GTREFCLK summary is provided for the whole system in the IPI Block Design canvas. Note that this command must be executed each time for a given Block design in case of a Vivado Project that has multiple Block Designs. REFCLK summary is generated per BD. If a system has multiple BDs, REFCLK summary must be generated separately. This table can be obtained by entering the following command in the Tcl console.

xilinx::designutils::report_gt_refclk_summary

Upon executing the command, <BD_name>_gt_refclk_summary.txt is generated in below path

Figure 1. GT Reference clock summary file location

It reports GT Reference Clocks, its frequencies, and source in this design shown in Figure 2.

Figure 2. Example 1 GT Reference Clock Summary Table

Example 2

The following figure shows four instances of x2 IPs sharing two GT Quads. In this case, four GTREFCLKs are available in the design. Because these four instances are of the same IP, GTREFCLK frequencies are same for all IPs. System designer can potentially drive these with the same GTREFCLK if GT Quads are placed adjacent to each other and use single input pin. This figure shows the GTREFCLK summary of this design:

Figure 3. Multiple Bridge IPs sharing GT Quads

Figure 4. Example 2 GT Reference Clock Summary Table

Based on the summary table, the GT REFCLK on the quads can be connected through a single utility buffer as shown in the following figure.

Figure 5. Modified Reference Clock Connections for Multiple Bridge IPs Sharing GT Quads