IP Integrator (IPI) Design Entry for Custom IP - 1.1 English

Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331)

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1.1 English

The design entry for Custom IP is through Bridge IP (gt_bridge_ip). Custom IPs are not required to be packaged in IP integrator. You need to input your requirements in the Bridge IP and use block automation to generate single or multi GT Quad designs. Generate the top file and hook it up with the custom IP. The Bridge IP GUI entry is a replica of GT Wizard (gt_quad_base). As a result, the values entered in the Bridge IP GUI are auto-propagated to GT Quad/s during system generation.

You can add gt_bridge_ip in IP integrator. Double-click on the IP symbol to open the Bridge IP GUI. Enable Pass Through Mode by selecting this option in the GUI. This brings out essential GT parallel interface to the user interface. Configure other parameters (gt_quad_base parameters are programmable through gt_bridge_ip GUI), including the number of lanes.

Main GUI Configuration Tab
The Main GUI Configuration tab provides customization options for transceiver preset selection, direction, master clock source, and number of lanes. The Main GUI tab is shown in the following figure:
Figure 1. Bridge IP GUI
Component Name
The name of the generated IP is set in the Component Name field. The default name is gt_bridge_ip_0.
Pass Through Mode
Selection of this option brings out essential GT parallel interface to the user interface.
Master Reset Enable
Enables Master reset logic in GT Quad. It is enabled by default. Do not disable this option.
Standard protocol presets are supported. Selecting a preset loads corresponding transceiver settings in sub GUI. multi-line rate presets can be loaded in this Preset window. It would populate multiple single line rate presets in the corresponding sub GUI. For example, multi-line rate presets with the suffix MLR are added to preset lists.
GT Direction
Select GT direction options given in the drop-down menu.
Number of Lanes
Select the required number of GT lanes. In the case of GTME5 configurations requiring user data widths of 320/512 when the line rate is greater than 56Gbps, the number of lanes added on the quad is treated as the number of active pcs channels because both the pcs lanes are used.
TX RX Master Clock Source
Select desired master clock source options given in the drop-down menu.
Transceiver Configs
Opens a pop-up Sub GUI in which transceiver transmitter and receiver settings can be configured. For more information, see Sub GUI Configuration Tab.
The following figure shows the design generated for Bridge IP in pass through mode using block automation.
Figure 2. Bridge IP Connections in Pass Through Mode
After the design creation, make all the essential ports as required by the custom IP on the bridge IP external to the block design. Create an HDL wrapper on the block design and interface the bridge IP signals with the custom IP.