Limitations of the Example Design - 1.1 English

The example design is the recommended means of simulating or implementing an instance of the Wizard IP core outside the context of your own system. It is quite simplistic, and you need to understand the following limitations:

• The example design does not implement specific protocols to generate or check data. Fundamentally, raw PRBS data is generated and checked.
• When the example design is simulated using the provided test bench, each transceiver channel is looped back from the serial data transmitter to the receiver. Data integrity can only be properly checked if the transmitter and receiver are configured for the same line rate and to use the same data coding. No rate adjustment schemes are used. If the transmitter and receiver line rates or data coding are configured differently in your system, cross-couple two appropriately-customized core instances and check for data integrity in hardware or in your own test bench. In such a setup, the transmitter of core instance A is rate and coding-matched to the receiver of core instance B, and vice-versa.
• Example designs are not provided for Multi-Quad designs.
• The example design is not guaranteed to achieve data integrity for the configurations where the user modified the value of outclk frequency shown in the GUI. It is because the value of BUFG GT dividers in the outclk to usrclk path in the example design needs to be adjusted accordingly.
  Figure 1. Transceiver Configuration Example
  For this configuration, the default value of OUTCLK frequency is 322.266 MHz. If you configure OUTCLK frequency as 644.531 MHz, the BUFG GT divider value needs to be adjusted by the user accordingly for the BUFG GT to drive 322.266 MHz as USRCLK to GT Quad.