gpio_enable Port Usage - 1.1 English

Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331)

Document ID
PG331
Release Date
2023-10-24
Version
1.1 English

gpio_enable port is used when multi-line rate IP switches from one line rate to another along with new reference clock values but with the same reference clock source. For example, assume that an IP is configured with two line rates, the first configuration with line_rate0, REFCLK0, and the second with line_rate1, REFCLK1. In this case, when an IP is switching from line_rate0 to line_rate1, the reference clock value also changes. In such scenarios, you need to assert gpio_enable signal, switch to the new reference clock frequency and ensure it is stable, and then toggle *rate_sel port. After toggling *rate_sel port, Bridge IP generates a gpi signal to GT Quad and handles gpi/gpo sequencing without user interference. gpio_enable can be deasserted after *resetdone is asserted high. The following figure shows gpio_enable usage in such scenarios:

Figure 1. Simulation Waveform for Line Rate and REFCLK Frequency Changes