You are expected to create package pin constraints for each instantiated transceiver differential reference clock buffer primitive as well as each instantiated differential recovered clock output buffer primitive if used. The constraints reflect the transceiver primitive site locations.
The MGT reference clock frequency must be constrained at
the Vivado Project top level XDC file at specified
frequency, that is, for GTHE4 and GTYE4: create_clock -period
2.223 [get_ports <DRU/FRL REFCLK portname>]