Connecting an UltraScale+ GT NORTH Reference Clock to a CPLL - 1.0 English

The HDMI PHY Controller opens the North and South reference clocks ports differently, depending on with which PLL they are associated. Additional ports with suffix 00 and 01 are opened when a reference clock is used with QPLL0/1. See Connecting an UltraScale+ GT South Reference Clock to a QPLL0/1.

When a reference clock is used with CPLL, the HDMI PHY Controller core opens two input ports, a GT channel or CPLL clock and a fabric clock (suffix odiv2). For example, NORTHREFCLK1 is used with CPLL, HDMI PHY Controller core opens the following input ports:

gtnorthrefclk1_in

This port is the GT Channel or CPLL clock and must be connected to the IBUF_OUT port of the IBUFDSGTE GT input clock buffer. See the following figure.

gtnorthrefclk1_odiv2_in

This port is the fabric clock and must be connected to the BUFG_GT_O port of the BUFG_GT buffer, which is being driven by the IBUF_DS_ODIV2 output of IBUFDSGTE GT input clock buffer. See the following figure.

Figure 1. North Reference Clock